Wafer Level Packaging-Wafer Level Packaging-Jiangsu Prosper Semiconductor INC.
PACKAGING SERVICE

Wafer Level Packaging

—— JPSI Semiconductor has a number of invention patents in the field of ultra-high vacuum and ultra-high temperature. Provide customers with "infrared thermal imaging wafer level full series vacuum sealing test service" with independent core technology
—— JPSI can provide 1280x1024 high-level wafer level package

Service Hotline:051262895811

Speciality

1) The packaging processing efficiency is high. It is manufactured by the batch production process in the form of wafers, which greatly improves the packaging efficiency by completing the packaging of the entire wafer chip at one time.

2) It has the advantages of flip chip packaging, namely light, thin, short and small. The package size is close to the chip size, and there is no limit on the height of the shell.

3) The IC design stage and packaging design of packaging chips can be considered uniformly and simultaneously, which will improve the design efficiency and reduce the design cost.

4) The equipment can make full use of wafer manufacturing equipment, without the need for back-end chip packaging production line construction.

5) Small package size and short lead lead bring better electrical performance.

6) When cutting into a single chip, the package structure or materials affect the scribing efficiency and the finished product rate.


Use

  • electronic product

  • Medical equipment

  • data transmission system

  • Vehicle navigation, tire pressure monitoring system, etc


Characteristics



Contact Us
Address: No.13, Dongjing Industrial Park, No.8, Dongfu Road, Suzhou Industrial Park
Phone: 0512-62895811
Fax: 0512-62895862
手机:

Business Department Manager Zhou:18921110830

Marketing Manager Yan:17551035333

E-mail: dm@jprosemi.com
Copyright © 2021 Jiangsu Prosper Semiconductor INC. 苏ICP备2022025005号-1
Technical support: Wanhe Technology