Semiconductor Packaging Overview
In recent years, the production capacity of the semiconductor industry has shifted significantly to Asia, the accelerated development of the semiconductor industry has risen to a national strategy, and all chips require packaging and testing, resulting in a broad market
| Stage | Time | Package form | Specific forms |
| Phase I | Before the 1970s | Through-hole tracing type package | Transistor package (TO), Ceramic double in-line package (COIP), Plastic double in-line package (POIP), Single in-line package (SIP) |
| Phase II | After the 1980s | Surface mount package | Plastic leaded chip carrier package (PLCC), plastic quad-lead flat package (PQFP), small form factor surface package (SOP), leadless quad flat package (PQFN), small form factor transistor package (SOT), double-sided flat pinless package (DFN) |
| Stage 3 | After the 1990s | Ball Grid Array Package (BGA) | Plastic Ball Array Package (PBGA), Ceramic Ball Array Package (CBGA), Ball Array Package with Heat Sink (EBGA), Flip Chip Ball Array Package (FC-BGA) |
Wafer Level Packaging (WLP) | Wafer Level Packaging (WLP) |
| Chip Scale Packaging (CSP) | Leadframe CSP package, flexible insert board CSP package, rigid insert board CSP package, wafer-level CSP package |
| Phase 4 | Beginning of the late 20th century | Multi-chip assembly (MCM) | Multilayer ceramic substrate (MCM-C), multilayer film substrate (MCM-D), multilayer printed circuit board (MCM-L) |
System level packaging (SIP) |
Three-dimensional packaging (3D) |
Bumping on chip |
| Phase 5 | The first decade of the 21st century began | Chip-level single-chip packaging (SoC) |
Micro Electro Mechanical Systems Packaging (MEMS) |
| Wafer Level System Packaging - Silicon Through Hole (TSV) |
| Flip-Chip Solder Package (FC) |
| Surface activated room temperature connection (SAB) |
| Fan-out IC package (Fan-Out) |
Rapid growth in the semiconductor market
IC packaging and testing is an essential part of the semiconductor industry chain, which is divided into packaging and testing segments. The global advanced packaging market will have an operating revenue of approximately US$31.5 billion in 2020; the advanced packaging market in China will reach US$4.6 billion in 2020, with a compound annual growth rate of 16%.
The rapid increase in domestic semiconductor design and foundry manufacturers has led to a shortage of advanced packaging and testing capacity.
In 2020, flip-chip (FLIP-CHIP) accounts for 81% of the advanced packaging market. Among the various advanced packaging platforms, 3D IC stacking and fan-out packages will grow at a rate of approximately 26%. Mobile and consumer applications account for 84% of the total advanced packaging market. It will account for 72% of the total advanced packaging by 2024. While in terms of revenue, telecom and infrastructure is the fastest growing segment in the advanced packaging market (~28%), its market share will grow from 6% in 2018 to 15% in 2024. Meanwhile, the automotive and transportation segment is expected to grow its market share from 9% in 2018 to 11% in 2024.
Control the market, cut into the pain point
The number of semiconductor design companies in China stood at 1,698 in 2018, an increase of 149% compared to 2014. The rapid growth of Chinese semiconductor design companies has driven the demand for local wafer and packaging foundries. Pure wafer sales grew at 41%, eight times the growth rate of the global pure wafer foundry market. Packaging and testing capacity is in short supply.
With the rapid increase in wafer fab production capacity, packaging capacity has become a bottleneck for incremental volume, packaging equipment domestic self-research that Li is particularly weak, the improvement of packaging yield has become a key link in the semiconductor industry to increase volume and reduce costs.
Pain Points
Global semiconductor production capacity are insufficient
Chinese semiconductor production capacity is more scarce
Pain Points
Insufficient self-research capability of semiconductor equipment
Mature mass production process to be improved
Pain Points
Packaging and testing as a bottleneck in the semiconductor industry
Advanced packaging and testing is still in its infancy
Pain Points
Reduce costs by improving packaging yields
Research and development of new materials and processes
Seize the market capacity opportunity and rapidly promote the expansion of four major packaging mass production lines
The number of semiconductor design companies in China stood at 1,698 in 2018, an increase of 149% compared to 2014. The rapid growth of Chinese semiconductor design companies has driven the demand for local wafer and packaging foundries. Pure wafer sales grew at 41%, eight times the growth rate of the global pure wafer foundry market. Packaging and testing capacity is in short supply.
With the rapid increase in wafer fab production capacity, packaging capacity has become a bottleneck for incremental volume, packaging equipment domestic self-research that Li is particularly weak, the improvement of packaging yield has become a key link in the semiconductor industry to increase volume and reduce costs.
Thermal image sensor class
Full range of thermal imaging detector packaging lines, covering metal, ceramic, and wafer-level packaging
2021 Extended packaging process, wafer-level packaging + movement assembly and testing
2022 Technology iteration to 1280x1024 wafer-level packaging process
2022 Development of flexible and rigid board + IR chip packaging and IR chip flip-chip soldering technology.
2021 Self-developed thermopile type GLCC package
2022 Development of thermopile-type wafer-level thermopile packages
Vacuum class
2021~22, Put in (vacuum+TO) and (vacuum+ceramic) package, vacuum degree 1.5x10-3pa provide
low cost, high yield, short lead time for temperature measurement and imaging products
2022 Self-developed vacuum energy storage encapsulation machine to shorten sealing and soldering time
2023 Reach 10 million/year vacuum storage welding production
IC plastic sealing class
2021 Construction of additional military grade plastic sealing mass production line completed.
2022 Add plastic CLCC, LQFP (thin) QFN. on board package IR chip.
2022 Mass Production Thermal Imaging Chip Molding Technology.
2023 Augmented plastisol 2 lines.
Advanced Packaging Class
Laser light source package
2022 High-precision micro-miniature laser package precision up to 10um or less. (Optical waveguide + Ling mirror + chip assembly)
2023 First domestic high-precision laser light source packaging plant.
Pressure sensor package
SIP multi-chip package
HD micro-optical packaging / RF device packaging
Open up the whole industry chain of chip manufacturing
Control the market, cut into the pain point
Investment Highlights
Domestic exclusive thermal imaging metal, ceramic and wafer full discipline
Sealing machine production foundry
Precision Molding, MEMS Sealing, High Vacuum Sealing, SIP, etc.
Advanced Packaging and Testing (APT) covers all four major packaging and testing areas
The team has over 18 years of experience in packaging and testing, and has developed its own packaging machine.
Standardized mass production process, leading yield rate in China
